Insulated gate semiconductor device

ABSTRACT

In a semiconductor device having a trench type insulated gate structure, in the case where a drift layer  2  of an n− conduction type has a high carrier density, when a high voltage is applied between a drain and a source in such a manner that a channel is not formed, the electric field strength of an insulator layer  9  below the trench type insulated gate is increased, thus causing breakdown. The withstand voltage of the semiconductor device is limited by the breakdown of the insulator layer  9 , and it is difficult to realize high withstand voltage. 
     In the characteristic of the present invention, a field relaxation semiconductor region 1 of a conduction type opposite to the conduction type of the drift layer  2  is formed within the drift layer  2  below the insulator layer  9  in the trench of the trench type insulated gate semiconductor device. Also, the thickness of a bottom portion of the insulator layer  9  provided in the trench of the trench type insulated gate semiconductor device is made significantly greater than the thickness of a lateral portion thereof.

TECHNICAL FIELD

The present invention relates to an insulated gate semiconductor deviceused as a switching device.

BACKGROUND ART

Conventionally, MOSFET and Insulation Gate Type Bipolar Transistor(hereinafter referred to as IGBT ) are well known as vertical type powersemiconductor devices which have advantages in high speed switchingcharacteristics, high input impedance and low input loss. In order toreduce the resistance of the junction field effect transistor(hereinafter referred to as JFET) immanent in above individualsemiconductor devices and establish low-loss, what are used for bothtransistors are semiconductor devices having a trench type insulatedgate structure having a gate 14 in the concave portion 29 as shown inFIGS. 11 and 12.

In such conventional semiconductor devices having a trench typeinsulated gate structure as shown in FIGS. 11 and 12, in case that thecarrier density in the n− conduction type drift layer 2 as asemiconductor substrate having the first conduction type (n) is larger,the formation of a channel is blocked by making the gate electricpotential smaller than the source electric potential (equivalent to theemitter electric potential in FIG. 12). In this case, if a high voltagehaving straight polarity is applied between the drain and the source(equivalently between the collector and the emitter in FIG. 12), adepletion layer is developed at the junction between the n− conductiontype drift layer 2 and the p conduction type body layer 4 as asemiconductor layer formed on a surface portionially or wholly of thesemiconductor substrate with the first conduction type, having thesecond conduction type (p) opposite to the first conduction type (n) andforming a junction with the n− conduction type drift layer 2.

However, as the carrier density of the n− conduction type drift layer 2is high below the gate 14 and the electric conductivity is larger, theresistance of the layer becomes smaller. As a result, the voltageapplied at the n− conduction type drift layer 2 becomes smaller, andthus, a high voltage is applied at the bottom portion of the insulationlayer 9 formed in the inner surface of the concave portion 29. Owing tothis characteristic, as the electric field strength at the bottomportion in the insulation layer 9 at the bottom portion of the trenchtype insulated gate becomes higher, the withstand voltage of theinsulator layer 9 is bound at most up to the level at the insulationbreakdown, and hence, the high-voltage adaptability of the device cannot be easily established. In addition, as the higher electric fieldstrength in the insulator layer 9 leads to the deterioration of theinsulator layer 9, the establishment of higher reliability of devices isdifficult.

DISCLOSURE OF INVENTION

An object of the present invention is to provide a insulated gatesemiconductor device having high-voltage adaptability and highreliability which allows to relax the electric field strength at thebottom portion of the trench type insulated gate.

In order to solve the above described problems, in the presentinvention, a first semiconductor region having a second conduction typeformed in the semiconductor substrate, that is, a semiconductor regionfor the relaxation of the electric field is defined at the bottomportion of the trench type insulated gate.

A characteristic of the present invention is based on a insulated gatesemiconductor device having a semiconductor substrate having a firstconduction type, a semiconductor layer of the second conduction typeopposite to the first conduction type formed on the semiconductorsubstrate and forming a junction with the semiconductor substrate, atleast one concave portion penetrating the semiconductor layer andreaching and cutting portionially the semiconductor substrate, a firstsemiconductor region of the second conduction type formed in thesemiconductor substrate at the bottom portion of the concave portion, aninsulator layer formed on the internal surface of the concave portion, agate insulated by the insulator layer with the substrate and thesemiconductor layer and at least portionially formed in the concaveportion, a second semiconductor layer of the first conduction typeformed at the surface of the semiconductor layer of the secondconduction type with a designated depth at the peripheral area of thegate surrounded by the insulator layer in the semiconductor layer, afirst electrode formed on the semiconductor layer of the secondconduction type and the semiconductor region and defined to beelectrically conduction to the semiconductor layer of the secondconduction type and the semiconductor region, and a second electrodedefined at another portion of the semiconductor substrate.

According to the present invention, by means of forming a semiconductorregion below the trench type insulated gate of the trench type insulatedgate semiconductor device for the relaxation of the electric field, incase of applying a voltage with a straight polarity between the drainand the source (or between the collector and the emitter), if the driftlayer is a first conduction type in FIGS. 1 to 10, a depleted layerdevelops in the body layer of the second conduction type and the driftlayer of the first conduction type. On the other hand, at the bottom ofthe trench type insulated gate electrode, a depleted layer extends fromthe junction between the semiconductor layer for the relaxation of theelectric field and the drift layer of the first conduction type inresponsive to the voltage between the drain and the source (or betweenthe collector and the emitter), and the almost all of the appliedvoltage is supported by the semiconductor region for electric fieldrelaxation and the drift layer of the first conduction type. As aresult, the voltage assigned to the bottom portion of the insulatorlayer of the gate becomes smaller and the electric field strength of theinsulator layer is relaxed, and consequently, higher high-voltageadaptability or higher reliability of the semiconductor device can beachieved.

The word “trench” used in the present invention relates to a conceptincluding various types of holes and concave portions other thanchannels.

Another characteristic of the present invention is that the thickness ofthe insulator layer of the bottom portion of the trench type insulatedgate is made to be much larger than the thickness of the lateralinsulator layer. Owing to this structure, higher high-voltageadaptability or higher reliability of the semiconductor device can beachieved. In this case, by forming a semiconductor region for theelectric field relaxation much higher high-voltage adaptability orhigher reliability of the semiconductor device can be achieved.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 2 of the present invention.

FIG. 3 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 3 of the present invention.

FIG. 4 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 4 of the present invention.

FIG. 5 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 5 of the present invention.

FIG. 6 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 6 of the present invention.

FIG. 7 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 7 of the present invention.

FIG. 8 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 8 of the present invention.

FIG. 9 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 9 of the present invention.

FIG. 10 is a cross-sectional view of the insulated gate semiconductordevice of the embodiment 10 of the present invention.

FIG. 11 is a cross-sectional view of the insulated gate semiconductordevice of conventional MOSFET.

FIG. 12 is a cross-sectional view of the insulated gate semiconductordevice of conventional IGBT.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, an embodiment of the present invention will be described byreferring to the drawings.

The insulated gate semiconductor device of the present invention has thefollowing embodiment.

On a semiconductor substrate having a first conduction type, asemiconductor layer of a second conduction type opposite to the firstconduction type and forming a junction to the semiconductor substrate isformed, and additionally, a concave portion is defined so as topenetrate the semiconductor layer and reach and cut partially thesemiconductor substrate. A first semiconductor region of the secondconduction type is formed in the semiconductor substrate at the bottomportion of the concave portion. An insulator layer is formed on theinternal surface of the concave portion, and at least a portion of thegate insulated by the insulator layer with the semiconductor substrateand the semiconductor layer of the second conduction type is formed inthe concave portion. In addition, at the peripheral area of the gatesurrounded by the insulator layer in the semiconductor layer, a secondsemiconductor layer of the first conduction type is formed at thesurface of the semiconductor layer of the second conduction type at theperipheral area of the gate with a designated depth. In addition, afirst electrode is formed on the semiconductor layer of the secondconduction type and the second semiconductor region so as to beelectrically conduction to the semiconductor layer of the secondconduction type and the second semiconductor region, and a secondelectrode is defined at another portion of the semiconductor substrate.

Further, on the semiconductor substrate, there are provided an electricconductor layer having the conduction type identical to that ofsemiconductor substrate on the semiconductor layer having an electricconductivity higher than that of semiconductor substrate.

The electric conductivity of the second substrate region is higher thanthat of the portion of the semiconductor substrate forming a junction tothe semiconductor layer of the second conduction type.

A layer of the second conductivity is formed on the surface opposite tothe surface of the substrate having the junction.

The second semiconductor region of the third conduction type is definedso as to be separated from the concave portion in the semiconductorsubstrate.

A layer of the second conductivity is formed on the surface opposite tothe surface of the substrate having the junction, and the secondsemiconductor region of the third conduction type is defined so as to beseparated from the concave portion in the semiconductor substrate.

The second electrode is formed at the position on the semiconductorsubstrate kept at a designated distance from the first electrode.

The first semiconductor region of the second conduction type formed inthe semiconductor substrate is formed at the bottom portion of theconcave portion and at the lateral portion connected to the bottomportion.

Another insulated gate semiconductor device of the present invention hasthe following embodiment.

On a semiconductor substrate having a first conduction type, asemiconductor layer of a second conduction type opposite to the firstconduction type and forming a junction to the semiconductor substrate isformed, and additionally, a concave portion is defined so as topenetrate the semiconductor layer and reach and cut partially thesemiconductor substrate. An insulator layer having a bottom portionthicker than the lateral portion is formed on the internal surface ofthe concave portion, and at least a portion of the gate insulated by theinsulator layer with the semiconductor substrate and the semiconductorlayer of the second conduction type is formed in the concave portion. Inaddition, at the peripheral area of the gate surrounded by the insulatorlayer in the semiconductor layer, a second semiconductor layer of thefirst conduction type is formed at the surface of the semiconductorlayer of the second conduction type at the peripheral area of the gatewith a designated depth. In addition, a first electrode is formed on thesemiconductor layer of the second conduction type and the secondsemiconductor region so as to be electrically conduction to thesemiconductor layer of the second conduction type and the secondsemiconductor region, and a second electrode is defined at anotherportion of the semiconductor substrate.

A layer of the second conductivity is formed on the surface opposite tothe surface of the substrate having the junction.

As for the insulator layer formed on the inner surface of the concaveportion, the thickness of the insulator layer at the bottom portion ofthe insulator layer is about approximately 5 times to approximately 20times larger than the thickness of the insulator layer at the lateralportion of the concave portion.

The thickness of the insulator layer formed at the bottom portion of theconcave portion is between approximately 0.5 μand approximately 2 μ. Inthe present invention, the numerals shown above as approximately 5, 20and 0.5 should be interpreted to contain an range of approximately 20%error.

EMBODIMENTS

By referring to FIGS. 1 to 10, embodiments of the present invention willbe described.

Embodiment 1

FIG. 1 shows a cross-sectional view of the unit segment of n channelSiC(silicon carbide) MOSFET of withstand voltage 2500V class in theembodiment 1 of the present invention. In FIG. 1, TS is a sourceterminal, TD is a drain terminal, and TG is a gate terminal In thisembodiment, the segment width is 5 μm and its depth is 1 mm. Otherstructural specifications are defined as below. The n− conduction typedrift layer 2 is formed on the n+ conduction type drain layer 3 and itsthickness is approximately 20 μm. The thickness of the n+ conductiontype drain layer 3 is about 300 μm, the thickness of the p conductiontype body layer 4 is 4 μm, the junction depth of the p+ conduction typesource region 5 and the p conduction type electric field relaxationsemiconductor region 1 is individually 0.5 μm, the depth of the concaveportion, that is, trench 69 is 6 μm, and the width of the trench is 3μm, the thickness of the insulator layer 9 such as SiO2 (silicon oxide)formed in side the trench 96 is 0.1 μm at the bottom portion and lateralportion of the trench 69, respectively.

In this embodiment, the trench type insulated gate electrode 14 isshaped in a stripe extended in the depth direction vertical to thesurface of the drawing sheet. The projected shape of the trench may be acircular hole having a 3 μm diameter or a square other than a stripeextended in the depth direction vertical to the surface of the drawingsheet. The trenches are arranged at regular intervals, for example, with5 μm pitch. In case of a circular trench, trenches may be arranged on arectangular grid vertically and horizontally or on a staggered griddiagonally.

A specific method of fabricating the device of this embodiment isdescribed as below. At first, what is prepared is an n+ type SiC(silicon carbide) substrate 3 to be used as a drain region composed ofSiC with the density between 10¹⁸ atm/cm³ and 10²⁰ atm/cm³, for example,10¹⁹ atm/cm³. An n− conduction type drift layer 2 composed of SiC withthe density between 10¹⁵ atm/cm³ and 10¹⁶ atm/cm³, for example, 5×10¹⁶atm/cm³ is formed on the whole surface of the substrate 3 by vapor phaseepitaxy method and so on. Next, a p conduction type body layer 4composed of SiC with the density about 10¹⁶ atm/cm³ is formed on thedrift layer 2 by vapor phase epitaxy method and so on. An n+ conductiontype region 5 with the density about 10¹⁸ atm/cm³ is formed selectivelyas a source layer by nitrogen ion implantation method and so on.(phosphoric ion, etc. may be used instead of nitrogen ion.)

Next, as shown in FIG. 1, a comprehensive substrate including thesubstrate 3, the drift layer 2 and the body layer 4 is processed byanisotropic etching, and a trench (channel) 69 penetrating the pconduction type body layer 4 and with its bottom portion reaching the n−conduction type drift layer 2 is formed. A p conduction type electricfield relaxation semiconductor region 1 having the depth of 0.5 μm andthe density of approximately 10¹⁷ atm/cm³ is formed at the bottomportion by boron (or alternatively aluminum) ion implantation method andso on. Next, after forming an gate insulator film 9 composed of SiO2 onthe inner surface of the trench 69, poly-silicon is made to be depositedin the trench 69 as a gate region containing high-density phosphor, andthus, the gate region 14 is formed in the trench 69. For example, thedepth of the trench 69 is 6 μm, its width is 3 μm and its length is 1mm. This size is an example but can be modified if necessary. Byremoving excess poly-silicon on the surface of the substrate other thanthe poly-silicon in the trench 69, the trench type insulated gateelectrode 14 is formed. Finally, by means of aluminum (or alternativelynickel), a source electrode 11 is formed on the surface of the substrateand a drain electrode 10 is formed on the rear face of the substrate,and an insulated gate semiconductor device (MOSFET) is obtained. An ONresistance of this MOSFET device is about 30 mΩcm².

The device of this embodiment is an n channel SiC MOSFET, in which thegate voltage to be applied is so adjusted that the electric potential ofthe drain electrode 10 may be higher than the electric potential of thesource electrode 11 and that the electric potential of the trench typeinsulated gate electrode 14 may be higher than the electric potential ofthe source electrode 11. In case that the gate voltage becomes higherthan a designated threshold voltage, an n conduction type channel isformed on the surface of the p conduction type body layer 4 at thelateral of the trench type insulated gate electrode 14. Then, electronsflow from the n+ conduction type source region 5 through the channel tothe n− conduction type drift layer 2 and furthermore to the n+conduction type drain layer 3, and consequently, the semiconductordevice is turned on. In contrast, in case that the gate voltage is soadjusted that the electric potential of the trench type insulated gateelectrode 14 may be smaller than the electrode of the source electrode11, and that the electric potential of the drain electrode 10 may behigher than the electric potential of the source electrode 11, depletionlayers are extended at the both sides of the junction between the n−conduction type drift layer 2 and the p conduction type body layer 4.Owing to those depletion layer, the electric field strength can berelaxed and a high withstand voltage can be established for high voltageapplication.

In this embodiment, other than depletion layers extended at the bothsides of the junction 24, depletion layers are also developed at thejunction between the p conduction type electric field relaxationsemiconductor region 1 below the trench type insulated gate electrode 14and the n− conduction type drift layer 2, and thus, a high withstandvoltage can be established for high voltage application. Therefore,below the trench type insulated gate electrode 14, almost all of theapplied voltage is supported by the electric field relaxationsemiconductor region 1 and the n− conduction type drift layer 2. Hence,the voltage applied to the insulator layer 9 below the bottom portion ofthe gate becomes smaller and the electric field strength in theinsulator layer 9 is relaxed. Thus, the electric f field strength in thegate insulator layer 9 can be relaxed and a high withstand voltage canbe established for high voltage application, and the reliability of thegate insulator layer 9 can be also increased.

In the computational simulation, in case of a conventional trench typeinsulated gate MOSFET shown in FIG. 11, the trench type insulated gateelectrode 14 and the source electrode 11 are made short and the electricpotential of the source electrode 11 is set to be 0V and +2000V isapplied to the drain electrode 10, the electric field strength of theinsulator layer 9 composed of SiO2 at the bottom portion of the trenchtype insulated gate comes close to the value between 6 to 10 MV/cmequivalent to the breakdown electric field strength of SiO2, and thewithstand voltage of the semiconductor device is 2000V which isdetermined by the withstand voltage of the SiO2 insulation film. Incontrast, in case of such a device as MOSFET in this embodiment in whichthe electric field relaxation semiconductor region 1 is formed below thetrench type insulated gate 14, the electric field strength of the SiO2insulator layer 9 at the bottom portion and the lateral end portion ofthe trench type insulated gate is reduced by 15 to 30% in comparisonwith the conventional device. As a result, it is proved that thewithstand voltage of the semiconductor device increases from 2300V to2600V.

In the conventional device in which the electric field relaxationsemiconductor region 1 is not formed below the trench type insulatedgate 14, the voltage applied to the drain electrode 10 is supported bythe n− conduction type drift layer 2 and the insulator layer 9 at thebottom portion of the trench type insulated gate 14, and as the voltageapplied to the insulator layer 9 becomes larger and, consequently, theelectric field strength in the insulator layer 9 becomes larger and thewithstand voltage of the semiconductor device itself is determined bythe withstand voltage of the insulator layer. However, in case that theelectric field relaxation semiconductor region 1 is now formed below thetrench type insulated gate 14, the applied voltage is distributed andsupported by the electric field relaxation semiconductor region 1, then− conduction type drift layer 2 and the insulator layer 9 at the bottomportion of the trench type insulated gate. Specifically, almost wholeportion of the voltage applied between the drain and the source issupported by the neighboring region of the junction between the electricfield relaxation semiconductor region 1 and the n− conduction type driftlayer 2. Thus, the voltage applied to the insulator layer 9 at thebottom portion of the trench type insulated gate 14 becomes smaller, andconsequently, the electric field strength of the insulation layer 9becomes smaller. In case of the device having higher withstand voltage,as the electric field strength becomes specifically higher, the effectbrought by the structure in which the electric field relaxationsemiconductor region 1 is formed below the trench type insulated gatebecomes distinguished.

Embodiment 2

FIG. 2 is a cross-sectional view of the unit of n channel SiC IGBT inthe embodiment 2 of the present invention. In FIG. 2, TE is an emitterterminal, and TC is a collector terminal. In the structure of the devicein FIG. 2 the p conduction type collector layer 6 is formed instead ofthe n+ conduction type drain layer 3 in the embodiment 1. In thestructural specifications and fabrication method in the embodiment 2, adifference from the embodiment 1 is only that a SiC p+ conduction typesubstrate is used instead of a SIC n+ conduction type substrate, butother aspects are similar to the embodiment 1. The impurity density ofthe p+ conduction type substrate is between 10¹⁸ atm/cm³ and 10¹⁹atm/cm³.

In the operation of the n channel IGBT of this embodiment, at first, thegate voltage to be applied is so adjusted that the electric potential ofthe collector electrode 12 may be higher than the electric potential ofthe emitter electrode 11 and that the electric potential of the trenchtype insulated gate electrode 14 may be higher than the electricpotential of the emitter electrode 13. In case that the gate voltagebecomes higher than a designated threshold voltage, an n conduction typechannel is formed on the surface of the p conduction type body layer 4at the lateral of the trench type insulated gate electrode 14, and then,electrons flow from the n+ conduction type emitter region 7 through thechannel to the n− conduction type drift layer 2. With this operation,positive holes are injected from the p conduction type collector layer 6to the n− conduction type drift layer 2, and then, the device is turnedon. In this case, as a modulation in the electric conductivity isassociated, ON resistance of IGBT is very small in comparison with veryhigh ON resistance of MOSFET. In this embodiment, ON voltage is 1.5 Vfor the current 200A/cm² and ON resistance is 7.5 mΩcm². In case thatthe gate voltage is so adjusted that the electric potential of thetrench type insulated gate electrode 14 may be smaller than theelectrode of the emitter electrode 13, and that the electric potentialof the collector electrode 12 may be higher than the electric potentialof the emitter electrode 13, depletion layers are extended at the bothsides of the junction between the n− conduction type drift layer 2 andthe p conduction type body layer 4, and the electric field strength canbe relaxed and a high withstand voltage can be established for highvoltage application.

In this embodiment, other than the depletion layer supporting theapplied voltage, depletion layers are developed also below the trenchtype insulated gate electrode 14 at the junction between the pconduction type electric field relaxation semiconductor region 1 and then− conduction type drift layer 2, and thus, a high withstand voltage canbe established for high voltage application. Therefore, below the trenchtype insulated gate electrode 14, almost all of the applied voltage issupported by the electric field relaxation semiconductor region 1 andthe n− conduction type drift layer 2. Hence, the voltage applied to theinsulator layer 9 below the bottom portion of the gate becomes smallerand the electric field strength in the insulator layer 9 is relaxed.Thus, the reliability of the gate insulator layer 9 can be alsoincreased. In addition, the electric field strength in the gateinsulator layer 9 can be relaxed and a high withstand voltage can beestablished for high voltage application. In this embodiment, similarlyto the embodiment 1 for MOSFET, the electric field strength of theinsulator layer 9 at the bottom portion and the lateral end portion ofthe trench type insulated gate 14 is reduced by 15 to 30% in comparisonwith the conventional IGBT having a structure without an electric fieldrelaxation semiconductor region 1. Thus, also in this embodiment, as theelectric field strength in the insulator layer 9 is relaxed, a highwithstand voltage can be established for high voltage application, andthe reliability of the gate insulator layer 9 can be also increased. Forexample, it is proved that the withstand voltage of the semiconductordevice increases from 2300V to 2600V.

Embodiment 3

FIG. 3 shows a cross-sectional view of the unit segment of n channelSiC(silicon carbide) MOSFET of withstand voltage 2500V class in theembodiment 3 of the present invention. In this embodiment, the segmentwidth is 5 μm and its depth is 1 mm. Other structural specifications aredefined as below. The n− conduction type drift layer 2 is formed on then+ conduction type drain layer 3 and its thickness is approximately 20μm. The thickness of the n+ conduction type drain layer 3 is about 300μm, the thickness of the p conduction type body layer 4 is 4 μm, thejunction depth of the p+ conduction type source region 5 and the pconduction type electric field relaxation semiconductor region 1 isindividually 0.5 μm, the depth of the concave portion, that is, trench69 is 6 μm, and the width of the trench is 3 μm, the thickness of theinsulator layer 9 such as SiO2 (silicon oxide) formed in side the trench96 is 0.5 μm at the bottom portion and 0.1 μm lateral portion of thetrench 69, respectively. In this embodiment, the trench type insulatedgate electrode 14 is shaped in a stripe extended in the depth directionvertical to the surface of the drawing sheet. The projected shape of thetrench may be a circular hole having a 3 μm diameter or a square otherthan a stripe extended in the depth direction vertical to the surface ofthe drawing sheet. The trenches are arranged at regular intervals, forexample, with 5 μm pitch. In case of a circular trench, trenches may bearranged on a rectangular grid vertically and horizontally or on astaggered grid diagonally.

A specific method of fabricating the device of this embodiment isdescribed as below. At first, what is prepared is an n+ type SiC(silicon carbide) substrate 3 to be used as a drain region composed ofSiC with the density between 10¹⁸ atm/cm³ and 10²⁰ atm/cm³, for example,10¹⁹ atm/cm³. An n− conduction type drift layer 2 composed of SiC withthe density between 10¹⁵ atm/cm³ and 10¹⁶ atm/cm³, for example, 5×10¹⁶atm/cm³ is formed on the whole surface of the substrate 3 by vapor phaseepitaxy method and so on. Next, a p conduction type body layer 4composed of SiC with the density about 10¹⁶ atm/cm³ is formed on thedrift layer 2 by vapor phase epitaxy method and so on. An n+ conductiontype region 5 with the density about 10¹⁸ atm/cm³ is formed selectivelyas a source layer by nitrogen ion implantation method and so on.(phosphoric ion, etc. may be used instead of nitrogen ion.)

Next, as shown in FIG. 3, a comprehensive substrate including thesubstrate 3, the drift layer 2 and the body layer 4 is processed byanisotropic etching, and a trench (channel) 69 penetrating the pconduction type body layer 4 and with its bottom portion reaching the n−conduction type drift layer 2 is formed. A p conduction type electricfield relaxation semiconductor region 1 having the depth of 0.5 μm andthe density of approximately 10¹⁷ atm/cm³ is formed at the bottomportion by boron (or alternatively aluminum) ion implantation method andso on. Next, after forming an gate insulator film 9 composed of SiO2 onthe inner surface of the trench 69, poly-silicon is made to be depositedin the trench 69 as a gate region containing high-density phosphor, andthus, the gate region 14 is formed in the trench 69. For example, thedepth of the trench 69 is 6 ?m, its width is 3 ?m and its length is 1mm. This size is an example but can be modified if necessary. Byremoving excess poly-silicon on the surface of the substrate other thanthe poly-silicon in the trench 69, the trench type insulated gateelectrode 14 is formed. Finally, by means of aluminum (or alternativelynickel), a source electrode 11 is formed on the surface of the substrateand a drain electrode 10 is formed on the rear face of the substrate,and an insulated gate semiconductor device (MOSFET) is obtained. An ONresistance of this MOSFET device is about 30 mΩcm².

The device of this embodiment is an n channel SiC MOSFET, in which thegate voltage to be applied is so adjusted that the electric potential ofthe drain electrode 10 may be higher than the electric potential of thesource electrode 11 and that the electric potential of the trench typeinsulated gate electrode 14 may be higher than the electric potential ofthe source electrode 11. In case that the gate voltage becomes higherthan a designated threshold voltage, an n conduction type channel isformed on the surface of the p conduction type body layer 4 at thelateral of the trench type insulated gate electrode 14. Then, electronsflow from the n+ conduction type source region 5 through the channel tothe n− conduction type drift layer 2 and furthermore to the n+conduction type drain layer 3, and consequently, the semiconductordevice is turned on. In contrast, in case that the gate voltage is soadjusted that the electric potential of the trench type insulated gateelectrode 14 may be smaller than the electrode of the source electrode11, and that the electric potential of the drain electrode 10 ay behigher than the electric potential of the source electrode 1, depletionlayers are extended at the both sides of the junction between the n−conduction type drift layer 2 and the p conduction type body layer 4.Owing to those depletion layer, the electric field strength can berelaxed and a high withstand voltage can be established for high voltageapplication.

In this embodiment, other than depletion layers extended at the bothsides of the junction 24, depletion layers are also developed at thejunction between the p conduction type electric field relaxationsemiconductor region 1 below the trench type insulated gate electrode 14and the n− conduction type drift layer 2, and thus, a high withstandvoltage can be established for high voltage application. Therefore,below the trench type insulated gate electrode 14, almost all of theapplied voltage is supported by the electric field relaxationsemiconductor region 1 and the n− conduction type drift layer 2. Hence,the voltage applied to the insulator layer 9 below the bottom portion ofthe gate becomes smaller and the electric field strength in theinsulator layer 9 is relaxed. Thus, the electric field strength in thegate insulator layer 9 can be relaxed and a high withstand voltage canbe established for high voltage application, and the reliability of thegate insulator layer 9 can be also increased.

In the computational simulation, in case of a conventional trench typeinsulated gate MOSFET shown in FIG. 11, the trench type insulated gateelectrode 14 and the source electrode 11 are made short and the electricpotential of the source electrode 11 is set to be 0V and +2000V isapplied to the drain electrode 10, the electric field strength of theinsulator layer 9 composed of SiO2 at the bottom portion of the trenchtype insulated gate comes close to the value between 6 to 10 MV/cmequivalent to the breakdown electric field strength of SiO2. Incontrast, in case of such a device as MOSFET in this embodiment in whichthe electric field relaxation semiconductor region 1 is formed below thetrench type insulated gate 14 and the thickness of the bottom portion ofthe insulator layer 9 is made to be 0.5 μm and larger than the thicknessof the literal of the insulator layer 9, the electric field strength ofthe SiO2 insulator layer 9 at the bottom portion and the lateral endportion of the trench type insulated gate is reduced by 45 to 65% incomparison with the conventional device. As a result, it is proved thatthe withstand voltage of the semiconductor device increases from 2900Vto 3250V.

In the conventional device in which the electric field relaxationsemiconductor region 1 is not formed below the trench type insulatedgate 14, the voltage applied to the drain electrode 10 is supported bythe n− conduction type drift layer 2 and the insulator layer 9 at thebottom portion of the trench type insulated gate 14, and as the voltageapplied to the insulator layer 9 becomes larger and, consequently, theelectric field strength in the insulator layer 9 becomes larger.However, in case that the electric field relaxation semiconductor region1 is now formed below the trench type insulated gate 14, the appliedvoltage is distributed and supported by the electric field relaxationsemiconductor region 1, the n− conduction type drift layer 2 and theinsulator layer 9 at the bottom portion of the trench type insulatedgate. Specifically, almost whole portion of the voltage applied betweenthe drain and the source is supported by the neighboring region of thejunction between the electric field relaxation semiconductor region 1and the n− conduction type drift layer 2. Thus, the voltage applied tothe insulator layer 9 at the bottom portion of the trench type insulatedgate 14 becomes smaller, and consequently, the electric field strengthof the insulation layer 9 becomes smaller. In case of the device havinghigher withstand voltage, as the electric field strength becomesspecifically higher, the effect brought by the structure in which theelectric field relaxation semiconductor region 1 is formed below thetrench type insulated gate becomes distinguished.

Embodiment 4

FIG. 4 is a cross-sectional view of the unit of n channel SiC IGBT inthe embodiment 4 of the present invention. In the structure of thedevice in FIG. 4, the p conduction type collector layer 6 is formedinstead of the n+ conduction type drain layer 3 in the embodiment 1. Inthe structural specifications and fabrication method in the embodiment2, a difference from the embodiment 1 is only that a SiC p+ conductiontype substrate is used instead of a SIC n+ conduction type substrate,but other aspects are similar to the embodiment 1. The impurity densityof the p+ conduction type substrate is between 10¹⁸ atm/cm³ and 10¹⁹atm/cm³.

In the operation of the n channel IGBT of this embodiment, at first, thegate voltage to be applied is so adjusted that the electric potential ofthe collector electrode 12 may be higher than the electric potential ofthe emitter electrode 11 and that the electric potential of the trenchtype insulated gate electrode 14 may be higher than the electricpotential of the emitter electrode 13. In case that the gate voltagebecomes higher than a designated threshold voltage, an n conduction typechannel is formed on the surface of the p conduction type body layer 4at the lateral of the trench type insulated gate electrode 14, and then,electrons flow from the n+ conduction type emitter region 7 through thechannel to the n− conduction type drift layer 2. With this operation,positive holes are injected from the p conduction type collector layer 6to the n− conduction type drift layer 2, and then, the device is turnedon. In this case, as a modulation in the electric conductivity isassociated, ON resistance of IGBT is very small in comparison with veryhigh ON resistance of MOSFET. In this embodiment, ON voltage is 1.5 Vfor the current 200A/cm² and ON resistance is 7.5 mΩcm². In case thatthe gate voltage is so adjusted that the electric potential of thetrench type insulated gate electrode 14 may be smaller than theelectrode of the emitter electrode 13, and that the electric potentialof the collector electrode 12 may be higher than the electric potentialof the emitter electrode 13, depletion layers are extended at the bothsides of the junction between the n− conduction type drift layer 2 andthe p conduction type body layer 4, and the electric field strength canbe relaxed and a high withstand voltage can be established for highvoltage application. In this embodiment, other than the depletion layersupporting the applied voltage, depletion layers are developed alsobelow the trench type insulated gate electrode 14 at the junctionbetween the p conduction type electric field relaxation semiconductorregion 1 and the n− conduction type drift layer 2, and thus, a highwithstand voltage can be established for high voltage application.Therefore, below the trench type insulated gate electrode 14, almost allof the applied voltage is supported by the electric field relaxationsemiconductor region 1 and the n− conduction type drift layer 2. Hence,the voltage applied to the insulator layer 9 below the bottom portion ofthe gate becomes smaller and the electric field strength in theinsulator layer 9 is relaxed. Thus, the reliability of the gateinsulator layer 9 can be also increased. In addition, the electric fieldstrength in the gate insulator layer 9 can be relaxed and a highwithstand voltage can be established for high voltage application. Inthis embodiment, similarly to the embodiment 1 for MOSFET, the electricfield strength of the insulator layer 9 at the bottom portion and thelateral end portion of the trench type insulated gate 14 is reduced by45 to 65% in comparison with the conventional IGBT having a structurewithout an electric field relaxation semiconductor region 1. Thus, alsoin this embodiment, as the electric field strength in the insulatorlayer 9 is relaxed, a high withstand voltage can be established for highvoltage application, and the reliability of the gate insulator layer 9can be also increased. For example, it is proved that the withstandvoltage of the semiconductor device increases from 2900V to 3250V.

Embodiment 5

FIG. 5 shows a cross-sectional view of the unit segment of n channelSiC(silicon carbide) MOSFET in the embodiment 5 of the presentinvention. In the structure of the device of the embodiment 5, a secondelectric field relaxation semiconductor region 8 is additionally formedas the third semiconductor region having the second conduction type (p)in the n conduction type channel SiC MOSFET in the embodiment 3. Theelectric field relaxation semiconductor region 8 has a 0.5 mm thicknessand its surface impurity density is 10¹⁷ atm/cm³ having the p conductiontype opposite to the n− conduction type drift layer 2. Fabricationmethod up to forming the n− conduction type drift layer 2 in thisembodiment is similar to that for MOSFET in the embodiment 3. Majordifference in the fabrication method from the embodiment 3 is that,after forming the n− conduction type drift layer 2, and the secondelectric field relaxation semiconductor region 8 is formed by injectingselectively boron (or alternatively aluminum) with ion implantationmethod and so on. The fabrication procedures after this process iscompletely equivalent to those in the embodiment 3, and their detaileddescription will be cut out.

In MOSFET of the embodiment 3, as the electric field strength of theinsulator layer 9 at the literal end portion of the bottom of the trenchtype insulated gate 14 becomes larger, the withstand voltage of thedevice itself is determined by the electric field strength of thisportion. In contrast, in the device formed with the second electricfield relaxation semiconductor region 8 as in this embodiment, thedepletion layer is developed at the junction between the second electricfield relaxation semiconductor region 8 and the drift layer 2, andconnected to the depletion layer formed at the junction between theelectric field relaxation semiconductor region 1 below the trench typeinsulated gate 14 and the n− conduction type drift layer 2. Thisdepletion layer extends in the n− conduction type drift layer 2 to theside of the drain electrode 10. As a result, the voltage applied betweenthe drain electrode and the source electrode is supported also by theextended depletion layer. Consequently, the voltage supported by theinsulator layer 9 becomes further smaller ad the electric field strengthbecomes further relaxed. In this embodiment, the electric field strengthis relaxed by 55% to 80% in comparison with the conventional device.Therefore, the withstand voltage increases by about 55% or more in thesemiconductor device in comparison with the conventional device, and,for example, the withstand voltage is improved from 3100V up to 3600V.Owing to the relaxation of the electric field strength described above,the reliability of the insulator layer 9 can be further increased. Inthe experimental result with 3000V application test, the lifetime of thedevice extends two times larger than the conventional device.

Embodiment 6

FIG. 6 shows a cross-sectional view of the segment of n channelSiC(silicon carbide) IGBT in the embodiment 6 of the present invention.In the embodiment 6, the device has a structure that a second electricfield relaxation semiconductor region 8 is formed in the n channel SiCIGBT. This structure is one that a p+ conduction type collector layer 6is formed instead of the n+ conduction type drain layer 3 in theembodiment 3. In the structural specifications and fabrication method ofthe embodiment 6, a p conduction type SiC substrate is used instead ofthe n conduction type SiC substrate used in the embodiment 5 and thedensity of the drain layer is made to be slightly smaller and thethickness and the film quality of the insulator layer 9 is increased.The impurity density of the p+conduction type substrate is between 10¹⁸atm/cm³and 10¹⁹ atm/cm³. In this embodiment, similarly to the embodiment5, the effect by forming the second electric field relaxationsemiconductor region 8 can be seen as the relaxation of the electricfield strength in the insulator layer 9. In this embodiment, theelectric field strength is relaxed by approximately 65% to 130% incomparison with the conventional device. Therefore, the withstandvoltage is increased by about 25% or more in this semiconductor device,and the withstand voltage can be increased from 3300V to 4600V. Owing tothe relaxation of the electric field strength described above, thereliability of the insulator layer 9 can be increased.

Embodiment 7

FIG. 7 shows a cross-sectional view of the unit segment of n channelSiC(silicon carbide) MOSFET in the embodiment 7 of the presentinvention. In the embodiment 7, the drain electrode 19 is not formed onthe drain layer 3 as in the embodiments 1 to 4 but formed on the driftlayer 2 on which the body layer 4 is to be formed. The device havingsuch a structure is designated a horizontal-type insulated gatesemiconductor device. In this embodiment 7, instead of the p conductiontype body layer 4 used in the previous embodiments, a p conduction typebody region 40 having a definite region, for example, shaped in a stripeis formed. The n+ conduction type drain region 33 is formed at adefinite distance from the body region 40 on the drift layer 2. Thedrain electrode 19 is formed on the drain region 33.

It is preferable to form the drain electrode 19 at a definite distancefrom the insulated gate electrode 14 so as to be parallel to theinsulated gate electrode 14. One or more p conduction type terminationregion 15 is formed between the drain electrode 19 and the body region40, substantially parallel to the body region 40. The termination region15 is used for relaxing the concentration of the electric field at theend portion of the body region. The detailed structure other than theportions described above is similar to that shown in FIG. 1.

As the source terminal and the drain terminal are defined in theidentical direction in the horizontal-type insulated gate semiconductordevice, the wiring work is made to be easier when embedding the devicein hybrid IC's and so on. In addition, as the drain electrode 19 isformed in the individual semiconductor devices, the degree of freedom inconnecting devices increases.

The structure of the drain region and the drain electrode 19 describedin the embodiment 7 is applicable to the structure of the embodiment 5shown in FIG. 5.

By means that the p+ conduction type collector region corresponding tothe collector layer 6 in the embodiment 2 shown in FIG. 2, theembodiment 4 shown in FIG. 4 and the embodiment 6 show in FIG. 6 isformed on the surface on the body layer 4 and that a collector electrodeis formed in the collector region, the device of the embodiment 7 can beapplied to the devices in the embodiments 2, 4 and 6.

Embodiment 8

FIG. 8 shows a cross-sectional view of the unit segment of n channelSiC(silicon carbide) MOSFET in the embodiment 8 of the presentinvention. Though the structure of the device of the embodiment 8 isalmost the same as the structure in the embodiment, the shape of thecross-section of the electric field relaxation semiconductor region andits fabrication process is different from the embodiment 3. In theembodiment 8, after forming the trench 69, when the electric fieldrelaxation semiconductor region 1A is formed, the amount of boron ion tobe implanted is made to be higher than the embodiment 3. Owing to thisprocedure, the diffusion of boron in the horizontal direction in the n−conduction type drift layer 2 becomes more actively made at the both endportions of the bottom of the trench, and the electric field relaxationsemiconductor region 1A is so shaped that its side extension is largeand equivalent to its depth. As a result, the electric field strength ofthe insulator layer 9 at the literal end portion of the bottom of thetrench type insulated gate 14 is further relaxed, and higher withstandvoltage can be realized. This can be realized because the appliedvoltage is supported by the extended region of the electric fieldrelaxation semiconductor region 1A. For example, in contrast to thewithstand voltage 2900V to 3250V in the semiconductor device of theembodiment 3, the withstand voltage in the embodiment 8 shown in FIG.8is 3200V to 3500V, and in addition, the reliability of the device can beincreased. In the structure of the device shown in FIG. 8, ON resistanceis slightly increased, but there is no problem in practical use. Theelectric field relaxation semiconductor region 1A with its both sidesextended widely can be applied to the devices shown in the embodiments 1to 7.

The structure of the drain region and the drain electrode 19 shown inthe embodiment 7 before can be applied to the structure of theembodiment 8 shown in FIG. 8.

Embodiment 9

FIG. 9 shows a cross-sectional view of the unit segment of n channelSiC(silicon carbide) MOSFET of withstand voltage 2500V class in theembodiment 9 of the present invention. In this embodiment, the appliedvoltage support is increased by means of making the thickness of thebottom portion of the trench larger 20 times or more than the thicknessof the insulator layer 9 at the lateral of the trench 69. In thisembodiment, the width of the segment is 5 μm and its depth is 1 mm.Other structural specification is as described below. The n− conductiontype drift layer 2 is formed on the n+ conduction type drain layer 3 andits thickness is about 20 μm. The thickness of the n+30 conduction typedrain layer 3 is about 300 μm, the thickness of the p conduction typebody layer 4 is 4 μm, and the junction depth of the n+ conduction typesource region 5 is 0.5 μm, the depth of the concave portion, that is,trench 69 is 6 μm, the width of the trench is 3 μm, and the thickness ofthe insulator layer 9 composed of SiO2 (silicon oxide) formed in thetrench 69 is 1 mm at the bottom of the trench 69 and 0.1 mm at thelateral of the trench 69. In this embodiment, the trench type insulatedgate electrode 14 is shaped in a stripe extended in the depth directionvertical to the surface of the drawing sheet. The projected shape of thetrench may be a circular hole having a 3 μm diameter or a square otherthan a stripe extended in the depth direction vertical to the surface ofthe drawing sheet. The trenches are arranged at regular intervals, forexample, with 5 μm pitch. In case of a circular trench, trenches may bearranged on a rectangular grid vertically and horizontally or on astaggered grid diagonally.

A specific method of fabricating the device of this embodiment isdescribed as below. At first, what is prepared is an n+ type SiC(silicon carbide) substrate 3 to be used as a drain region composed ofSiC with the density between 10¹⁸ atm/cm³ and 10²⁰ atm/cm³, for example,10¹⁹ atm/cm³. An n− conduction type drift layer 2 composed of SiC withthe density between 10¹⁵ atm/cm³ and 10¹⁶ atm/cm³, for example, 5×10⁶atm/cm³ is formed on the whole surface of the substrate 3 by vapor phaseepitaxy method and so on. Next, a p conduction type body layer 4composed of SiC with the density about 10¹⁶ atm/cm³ is formed on thedrift layer 2 by vapor phase epitaxy method and so on. An n+ conductiontype region 5 with the density about 10¹⁸ atm/cm³ is formed selectivelyas a source layer by nitrogen ion implantation method and so on.(phosphoric ion is allowed instead of nitrogen ion.)

Next, as shown in FIG. 9, a comprehensive substrate including thesubstrate 3, the drift layer 2 and the body layer 4 is processed byanisotropic etching, and a trench (channel) 69 penetrating the pconduction type body layer 4 and with its bottom portion reaching the n−conduction type drift layer 2 is formed. Subsequently, a gate insulatorfilm 9 composed of SiO2 is formed on the inner surface of the trench 69,and the SiO2 gate insulator film 9 at the bottom of the trench isselectively developed by vapor phase epitaxy method until its thicknessreaches about 1 μm. Poly-silicon is made to be deposited in the trench69 as a gate region containing high-density phosphor, and thus, the gateregion 14 is formed in the trench 69. For example, the depth of thetrench 69 is 6 μm, its width is 3 m and its length is 1 mm. This size isan example but can be modified if necessary. By removing excesspoly-silicon on the surface of the substrate other than the poly-siliconin the trench 69, the trench type insulated gate electrode 14 is formed.Finally, by means of aluminum (or alternatively nickel), a sourceelectrode 11 is formed on the surface of the substrate and a drainelectrode 10 is formed on the rear face of the substrate, and aninsulated gate semiconductor device (MOSFET) is obtained. An ONresistance of this MOSFET device is about 30 mΩcm².

The device of this embodiment is an n channel SiC MOSFET, in which thegate voltage to be applied is so adjusted that the electric potential ofthe drain electrode 10 may be higher than the electric potential of thesource electrode 11 and that the electric potential of the trench typeinsulated gate electrode 14 may be higher than the electric potential ofthe source electrode 11. In case that the gate voltage becomes higherthan a designated threshold voltage, an n conduction type channel isformed on the surface of the p conduction type body layer 4 at thelateral of the trench type insulated gate electrode 14. Then, electronsflow from the n+ conduction type source region 5 through the channel tothe n− conduction type drift layer 2 and furthermore to the n+conduction type drain layer 3, and consequently, the semiconductordevice is turned on. In contrast, in case that the gate voltage is soadjusted that the electric potential of the trench type insulated gateelectrode 14 may be smaller than the electrode of the source electrode11, and that the electric potential of the drain electrode 10 may behigher than the electric potential of the source electrode 11, depletionlayers are extended at the both sides of the junction between the n−conduction type drift layer 2 and the p conduction type body layer 4.Owing to those depletion layer, the electric field strength can berelaxed and a high withstand voltage can be established for high voltageapplication.

In this embodiment, by means that the thickness of the insulator layer 9at the bottom of the trench is 1 μm, that is, several times or ten timeslarger than the thickness of the insulator layer 9 at the literal of thetrench, the electric field at the bottom portion and the literal endportion of the insulator layer 9 can be relaxed. Thus, the withstandvoltage of the device can be increased, or the reliability of the gateinsulator layer 9 can be increased.

In the computational simulation, in case of a conventional trench typeinsulated gate MOSFET shown in FIG. 11, the trench type insulated gateelectrode 14 and the source electrode 11 are made short and the electricpotential of the source electrode 11 is set to be 0V and +2000V isapplied to the drain electrode 10, the electric field strength of theinsulator layer 9 composed of SiO2 at the bottom portion of the trenchtype insulated gate is larger than the value between 6 to 10 MV/cmequivalent to the breakdown electric field strength of SiO2. Incontrast, in case of such a device as MOSFET in this embodiment in whichthe thickness of the insulator layer 9 is made to be 1 ?m, the electricfield strength of the SiO2 insulator layer 9 at the lateral end portionof the bottom portion of the trench type insulated gate is reduced by90% in comparison with the conventional device. The reliability of theinsulator layer decreases remarkably when the electric field strengthreaches its breakdown electric field strength. In this embodiment, asthe electric field strength of the insulator layer 9 becomes small to alarge extent, the reliability of the device itself increases much. As aresult, the withstand voltage of the semiconductor device increases from2900V to 3250V. In addition, by making the thickness of the n− driftlayer larger, much higher withstand voltage can be obtained. The appliedat the drain electrode 10 is supported by the n− conduction type driftlayer 2 and the insulator layer 9 at the bottom of the trench typeinsulated gate 14, and the fraction of the supported voltage at theinsulator layer 9 is larger and consequently, its electric fieldstrength is larger. However, by means that the thickness of theinsulator layer at the bottom of the trench type insulated gate 14 ismade to be about 1 μm or larger as in this embodiment, the appliedvoltage is supported by the n− conduction type drift layer 2 and theinsulator layer at the bottom portion of the trench type insulated gate,and especially, the major portion of the voltage applied between thedrain and the source are supported by the bottom portion of theinsulator layer 9. However, as the thickness of the insulator layer 9 isincreased, the electric field strength in the insulator layer 9 becomessmaller.

As the electric field strength in the insulator layer 9 at the bottom ofthe trench type insulated gate 14 is especially high in device havinghigher withstand voltage, the effect of making the thickness of thebottom portion of the insulator layer 9 arises remarkably.

In the embodiment 9, if applying the device structure corresponding tothe second electric field relaxation semiconductor region 8 in theembodiment 5, the effect brought by the device of the embodiment 5 canbe obtained.

In the embodiment 9, if forming the drain electrode 19 so as to belocated at a definite distance from the insulated gate electrode 14 andparallel to the insulated gate electrode 14 as defined in the embodiment7, the effect brought by the device of the embodiment 7 can be obtained.

Embodiment 10

FIG. 10 is a cross-sectional view of the unit of n channel SiC IGBT inthe embodiment 10 of the present invention. In the structure of thedevice in FIG. 4, the p conduction type collector layer 6 is formedinstead of the n+ conduction type drain layer 3 in the embodiment 9. Inthe structural specifications and fabrication method in the embodiment10, a difference from the embodiment 9 is only that a SiC p+ conductiontype substrate is used instead of a SIC n+ conduction type substrate,but other aspects are similar to the embodiment 9. The impurity densityof the p+ conduction type substrate is between 10¹⁸ atm/cm³ and 10¹⁹atm/cm³.

In the operation of the n channel IGBT of this embodiment, at first, thegate voltage to be applied is so adjusted that the electric potential ofthe collector electrode 12 may be higher than the electric potential ofthe emitter electrode 11 and that the electric potential of the trenchtype insulated gate electrode 14 may be higher than the electricpotential of the emitter electrode 13. In case that the gate voltagebecomes higher than a designated threshold voltage, an n conduction typechannel is formed on the surface of the p conduction type body layer 4at the lateral of the trench type insulated gate electrode 14, and then,electrons flow from the n+ conduction type emitter region 7 through thechannel to the n− conduction type drift layer 2. With this operation,positive holes are injected from the p conduction type collector layer 6to the n− conduction type drift layer 2, and then, the device is turnedon. In this case, as a modulation in the electric conductivity isassociated, ON resistance of IGBT is very small in comparison with veryhigh ON resistance of MOSFET. In this embodiment, ON voltage is 1.5 Vfor the current 200A/cm² and ON resistance is 7.5 mΩcm². In case thatthe gate voltage is so adjusted that the electric potential of thetrench type insulated gate electrode 14 may be smaller than theelectrode of the emitter electrode 13, and that the electric potentialof the collector electrode 12 may be higher than the electric potentialof the emitter electrode 13, depletion layers are extended at the bothsides of the junction between the n− conduction type drift layer 2 andthe p conduction type body layer 4, and the electric field strength canbe relaxed and a high withstand voltage can be established for highvoltage application.

In this embodiment, below the trench type insulated gate electrode 14,almost all of the applied voltage is supported by the bottom portion ofthe insulator layer 9, and by making the thickness of the bottom portionof the insulator layer 9 larger, the electric field length at the bottomportion and the lateral end portion can be relaxed. Thus, thereliability of the gate insulator layer 9 can be also increased. Inaddition, the electric field strength in the gate insulator layer 9 canbe relaxed and a high withstand voltage can be established for highvoltage application. In this embodiment, similarly to the embodiment 1for MOSFET, the electric field strength of the insulator layer 9 at thebottom portion and the lateral end portion of the trench type insulatedgate 14 is reduced by 90% in comparison with the conventional IGBThaving a structure without making the thickness of the gate insulatorlayer 9 larger. Thus, also in this embodiment, as the electric fieldstrength in the insulator layer 9 is relaxed, a high withstand voltagecan be established for high voltage application, and the reliability ofthe gate insulator layer 9 can be also increased. For example, it isproved that the withstand voltage of the semiconductor device increasesfrom 2900V to 3250V.

In the embodiment 10, if applying the device structure corresponding tothe second electric field relaxation semiconductor region 8 in theembodiment 6, the effect brought by the device of the embodiment 6 canbe obtained.

In the embodiment 10, if forming the collector electrode 12 so as to belocated at a definite distance from the insulated gate electrode 14 andparallel to the insulated gate electrode 14 as defined in the embodiment7, the effect brought by the device of the embodiment 7 can be obtained.

The embodiments 1 to 10 of the present invention has been described, butthe present invention is not limited to the devices in thoseembodiments, but applicable to trench type MOS thyristor, trench typestatic induction transistor, thyristor and IEGT (Injection EnhancedInsulated Gate Bipolar Transistor), and furthermore, variousmodifications and applications are allowable. The insulator layer 9 maybe composed of Ta2O5 (tantalum oxide), Si3N4 (silicon nitride) and AlN(aluminum nitride) other than SiO2. Though the gate in the embodimentsof the present invention is structured to be embedded with the trench,the structure of the gate is not necessarily limited to this but allowedto be formed as a thin film as a portion of the inner wall of the trenchwith the SiO2 insulator layer 9.

In the insulated gate semiconductor device in the present invention, bymeans that the first semiconductor region of the second conduction typeat the bottom of the trench type insulated gate, the electric fieldstrength which was high in the semiconductor device formed with theconventional trench type insulated gate structure can be relaxed. As aresult, the withstand voltage of the semiconductor device can beincreased by 15 to 30% in comparison with the conventional semiconductordevice. The relaxation of the electric field strength makes thereliability of the insulator layer increase.

In the insulated gate semiconductor device in the present invention, bymeans that the first semiconductor region of the second conduction typeat the bottom of the trench type insulated gate and that the thicknessof the insulator layer at the bottom of the trench type insulated gateis made to be larger than the thickness of the lateral portion of theinsulator layer, the electric field strength of the insulator layer atthe bottom portion of the trench type insulated gate which was high inthe semiconductor device formed with the conventional trench typeinsulated gate structure can be further relaxed. As a result, thewithstand voltage of the semiconductor device can be increased by 45 to65% in comparison with the conventional semiconductor device. Therelaxation of the electric field strength makes the reliability of theinsulator layer increase.

And furthermore, by means that the semiconductor substrate of theinsulated gate semiconductor device of the present invention is sostructured as to be formed on the substrate having higher conductivityand with the same of conduction type and with a layer having lowerconductivity, the contact resistance between the second electrode andthe semiconductor substrate can be reduced to be small. Thus, by forminga layer having lower conductivity, the withstand voltage of thesemiconductor device itself can be increased.

In addition, by means of making the conductivity of the secondsemiconductor region of the insulated gate semiconductor device of thepresent invention higher than the conductivity of the layer forming ajunction with the semiconductor layer having the second conduction typeforming a junction with the semiconductor substrate on the semiconductorsubstrate, the contact resistance between the first electrode and thesecond semiconductor region can be made small and ON resistance of thesemiconductor device can be reduced.

In the insulated gate semiconductor device having a semiconductor layerof the second conduction type on the rear face of the face having ajunction with the semiconductor substrate, by means of forming the firstsemiconductor region of the second conduction type at the bottom of thetrench gate, the electric field strength of the insulator layer at thebottom portion of the trench type insulated gate which was high in thesemiconductor device formed with the conventional trench type insulatedgate structure can be further relaxed. As a result, the withstandvoltage of the semiconductor device can be increased by 15 to 30% incomparison with the conventional semiconductor device. The relaxation ofthe electric field strength makes the reliability of the insulator layerincrease.

In the insulated gate semiconductor device having a semiconductor layerof the second conduction type on the rear face of the face having ajunction with the semiconductor substrate, by means of forming the firstsemiconductor region of the second conduction type at the bottom of thetrench gate and that the thickness of the insulator layer at the bottomof the trench type insulated gate is made to be larger than thethickness of the lateral portion of the insulator layer, the electricfield strength of the insulator layer at the bottom portion of thetrench type insulated gate which was high in the semiconductor deviceformed with the conventional trench type insulated gate structure can befurther relaxed. As a result, the withstand voltage of the semiconductordevice can be increased by 45 to 65% in comparison with the conventionalsemiconductor device. The relaxation of the electric field strengthmakes the reliability of the insulator layer increase.

By means that forming the third semiconductor region of the secondconduction type in the semiconductor substrate of the insulated gatesemiconductor device of the present invention, the electric fieldstrength of the insulator layer at the bottom portion of the trench typeinsulated gate can be relaxed much more than the case of forming onlythe first semiconductor region of the second conduction type. As aresult, the withstand voltage of the semiconductor device can beincreased by 55 to 130% in comparison with the conventionalsemiconductor device. The relaxation of the electric field strengthmakes the reliability of the insulator layer higher.

In the horizontal-type semiconductor device in which the secondelectrode is formed in the direction identical to the direction in whichthe first electrode is formed, the withstand voltage or the reliabilitycan be increased, and in addition, as the individual semiconductordevices have the second electrodes in an identical direction, the degreeof freedom in connecting devices increases and the degree of integrationcan increases.

By means that the first electric field relaxation semiconductor regionof the second conduction type is formed at the bottom portion of thetrench as well as the lateral portion connected to the bottom portion,the electric field strength of the insulator layer at the lateralportion at the bottom of the trench type insulated gate can be furtherrelaxed, and the withstand voltage can be increased. By means of therelaxation of the electric field strength of the insulator layer, thereliability of the insulator layer can be increased.

By means of making the thickness of the bottom portion of the insulatorlayer much larger than the thickness of the lateral portion of theinsulator layer, the electric field at the boundary between the bottomportion and the lateral portion of the insulator layer can be muchrelaxed, and the withstand voltage can be increased. By means of therelaxation of the electric field strength of the insulator layer, thereliability of the insulator layer can be increased.

In addition, by forming the first semiconductor region of the secondconduction type, further increase in the withstand voltage and thereliability can be established.

What is claimed is:
 1. A wide-gap semiconductor device comprising: asemiconductor substrate exhibiting a first conductivity type; asemiconductor layer exhibiting a second conductivity type opposite tosaid first conductivity type deposited on said semiconductor substrateand forming a junction to said semiconductor substrate; at least oneconcave portion penetrated through said semiconductor layer to reach andcut partially into said semiconductor substrate; a first semiconductorregion exhibiting said second conductivity type and having an impurityconcentration higher than that of said semiconductor substrate, formedin said semiconductor substrate at a bottom of said concave portion; aninsulator layer formed on an inner surface of said concave portion; agate insulated by said insulator layer with said semiconductor substrateand said semiconductor layer and at least partially formed in saidconcave portion; a second semiconductor region exhibiting said firstconductivity type formed at a surface of said semiconductor layer with adesignated depth at a peripheral area of said gate surrounded by saidinsulator layer in said semiconductor layer; a first electrode formed onsaid semiconductor layer and said second semiconductor region anddefined to be electrically conductive to said semiconductor layer andsaid second semiconductor region; and a second electrode defined atanother portion of said semiconductor substrate, wherein saidsemiconductor substrate has a first semiconductor layer formed onanother semiconductor layer having a higher electric conductivity, saidfirst semiconductor layer having a conductivity type identical to thatof said another semiconductor layer and an electric conductivity lowerthan that of said semiconductor layer.
 2. A wide-gap semiconductordevice comprising: a semiconductor substrate exhibiting a firstconductivity type; a semiconductor layer exhibiting a secondconductivity type opposite to said first conductivity type deposited onsaid semiconductor substrate and forming a junction to saidsemiconductor substrate; at least one concave portion penetrated throughsaid semiconductor layer to reach and cut partially into saidsemiconductor substrate; a first semiconductor region exhibiting saidsecond conductivity type and having an impurity concentration higherthan that of said semiconductor layer, formed in said semiconductorsubstrate at a bottom of said concave portion; an insulator layer formedon an inner surface of said concave portion; a gate insulated by saidinsulator layer with said semiconductor substrate and said semiconductorlayer and at least partially formed in said concave portion; a secondsemiconductor region exhibiting said first conductivity type formed at asurface of said semiconductor layer with a designated depth at aperipheral area of said gate surrounded by said insulator layer in saidsemiconductor layer; a first electrode formed on said semiconductorlayer and said second semiconductor region and defined to beelectrically conductive to said semiconductor layer and said secondsemiconductor region; and a second electrode defined at another portionof said semiconductor substrate, wherein said semiconductor substratehas a first semiconductor layer formed on another semiconductor layerhaving a higher electric conductivity, said first semiconductor layerhaving a conductivity type identical to that of said anothersemiconductor layer and an electric conductivity lower than that of saidsemiconductor layer.
 3. A wide-gap semiconductor device of claim 1,wherein said second semiconductor region has an electric conductivityhigher than that of a portion of said semiconductor substrate formingsaid junction to said semiconductor layer.
 4. A wide-gap semiconductordevice of claim 1, wherein said semiconductor layer exhibiting saidsecond conductivity type is formed on a surface opposite to the surfaceof said semiconductor substrate having said junction.
 5. A wide-gapsemiconductor device of claim 1, further comprising a thirdsemiconductor region exhibiting said second conductivity type formed insaid semiconductor substrate so as to be separated from said concaveportion.
 6. A wide-gap semiconductor device of claim 4, wherein saidsemiconductor layer exhibiting said second conductivity type is formedon a surface opposite to the surface of said semiconductor substratehaving said junction; and a third semiconductor region exhibiting saidsecond conductivity type is in said semiconductor substrate so as to beseparated from said concave portion in said semiconductor substrate. 7.A wide-gap semiconductor device of claim 1, wherein said secondelectrode is formed on said semiconductor substrate separated from saidfirst electrode by a designated distance.
 8. A wide-gap semiconductordevice of claim 1, wherein said first semiconductor region formed insaid semiconductor substrate is formed at a bottom of said concaveportion and at a lateral portion connected to the bottom of said concaveportion.
 9. A wide-gap semiconductor device of claim 2, wherein saidsecond semiconductor region has an electric conductivity higher thanthat of a portion of said semiconductor substrate forming said junctionto said semiconductor layer.
 10. A wide-gap semiconductor device ofclaim 2, wherein said semiconductor layer exhibiting said secondconductivity type is formed on a surface opposite to the surface of saidsemiconductor substrate having said junction.
 11. A wide-gapsemiconductor device of claim 10, wherein said semiconductor layerexhibiting said second conductivity type is formed on a surface oppositeto the surface of said semiconductor substrate having said junction; anda third semiconductor region exhibiting said second conductivity type isin said semiconductor substrate so as to be separated from said concaveportion in said semiconductor substrate.
 12. A wide-gap semiconductordevice of claim 2, further comprising a third semiconductor regionexhibiting said second conductivity type formed in said semiconductorsubstrate so as to be separated from said concave portion.
 13. Awide-gap semiconductor device of claim 2, wherein said second electrodeis formed on said semiconductor substrate separated from said firstelectrode by a designated distance.
 14. A wide-gap semiconductor deviceof claim 2, wherein said first semiconductor region formed in saidsemiconductor substrate is formed at a bottom of said concave portionand at a lateral portion connected to the bottom of said concaveportion.
 15. A wide-gap semiconductor device comprising: a semiconductorsubstrate exhibiting a first conductivity type; a semiconductor layerexhibiting a second conductivity type opposite to said firstconductivity type deposited on said semiconductor substrate and forminga junction with said semiconductor substrate; at least one concaveportion penetrated through said semiconductor layer to reach and cutpartially into said semiconductor substrate; a first semiconductorregion exhibiting said second conductivity type and having an impurityconcentration higher than that of said semiconductor substrate, formedin said semiconductor substrate at a bottom of said concave portion; aninsulator layer formed on an inner surface of said concave portion, andhaving a thickness larger than a lateral portion of said concave portionat the bottom of said concave portion; a gate insulated by saidinsulator layer with said semiconductor substrate and said semiconductorlayer and at least partially formed in said concave portion; a secondsemiconductor region exhibiting said first conductivity type formed at asurface of said semiconductor layer with a designated depth at aperipheral area of said gate surrounded by said insulator layer in saidsemiconductor layer; a first electrode formed on said semiconductorlayer and said second semiconductor region and defined to beelectrically conductive to said semiconductor layer and said secondsemiconductor region; and a second electrode defined at another portionof said semiconductor substrate.
 16. A wide-gap semiconductor device ofclaim 15, wherein said semiconductor layer exhibiting said secondconductivity is formed on a surface opposite to the surface of saidsemiconductor substrate having said junction.
 17. A wide-gapsemiconductor device comprising: a substrate exhibiting a firstconductivity type; a semiconductor layer exhibiting a secondconductivity type opposite to said first conductivity type deposited onsaid substrate; at least one trench having an opening in a surface ofsaid semiconductor layer and a depth extending through said substrate;an electric field relaxation region exhibiting said second conductivitytype and having an impurity concentration higher than that of saidsemiconductor layer, formed in said substrate below a bottom of saidtrench; an insulator layer formed on a surface of said trench; a gateelectrode deposited in said trench and insulated from said substrate andsaid semiconductor layer by said insulator layer; an electricalconduction region exhibiting said first conductivity type formed in saidsemiconductor layer surrounding said gate electrode insulated by saidinsulator layer; a source electrode formed on said semiconductor layerand said electrical conduction region; and a gate electrode formed atanother portion of said semiconductor substrate.
 18. A wide-gapsemiconductor device of claim 17, wherein said first conductivity typeis a n-type dopant, and said second conductivity type is a p-typedopant.
 19. A wide-gap semiconductor device of claim 17, furthercomprising another electric field relaxation region exhibiting saidsecond conductivity type formed in said substrate but separated fromsaid electric field relaxation region formed in said substrate below thebottom of said trench.
 20. A wide-gap semiconductor device of claim 17,wherein said electric field relaxation region has a depth of 0.5 micronsand a density of approximately 10¹⁷ atm/cm³ formed below the bottom ofsaid trench by either boron or aluminum ion implantation.